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	<title>ActiveSPLIT.com &#187; the fabulous logic analyzer</title>
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		<title>The Fabulous Logic Analyzer &#8211; Problems during port initialization</title>
		<link>http://www.activesplit.com/the-fabulous-logic-analyzer-problems-during-port-initialization/</link>
		<comments>http://www.activesplit.com/the-fabulous-logic-analyzer-problems-during-port-initialization/#comments</comments>
		<pubDate>Wed, 10 Feb 2010 19:02:47 +0000</pubDate>
		<dc:creator>Nik</dc:creator>
				<category><![CDATA[Electronics]]></category>
		<category><![CDATA[Microcontroller]]></category>
		<category><![CDATA[logic analyzer]]></category>
		<category><![CDATA[lpt]]></category>
		<category><![CDATA[parallel port]]></category>
		<category><![CDATA[parallel port initialization problem]]></category>
		<category><![CDATA[parallel port problem]]></category>
		<category><![CDATA[tfla]]></category>
		<category><![CDATA[the fabulous logic analyzer]]></category>

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		<description><![CDATA[&#8220;TFLA-01 is a simple logic analyzer for the PC.  This one consists of a simple schematic which is attached on the PCs parallel port (a real parallel port is highly recommended, not a USB adapter) and which can analyse H and L levels of 8 inputs. On the PC, there&#8217;s running a graphical program which [...]]]></description>
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